Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)
Original reporting by Semiconductor Engineering
The relentless pursuit of smaller, faster, and more efficient electronics drives innovation at the atomic scale. As traditional silicon-based transistors approach fundamental physical limits, the industry increasingly turns to two-dimensional (2D) materials, which offer the ultimate in channel thickness—just a single atom. However, realizing their full potential has been hampered by the difficulty of scaling these materials aggressively in length and width while maintaining high performance. Previous attempts often saw device efficacy degrade significantly when channels were narrowed, limiting their practical application in advanced computing.
A new fabrication path
Now, a collaborative team of researchers from Stanford University, Chalmers University of Technology, HORIBA Scientific, and SLAC National Accelerator Laboratory has unveiled a significant breakthrough. Publishing in *Nature Nanotechnology*, they detail the creation of monolayer 2D semiconductor nanoribbon transistors that achieve unprecedented scaling. Using a sophisticated top-down multipatterning process, including ingeniously designed "anchored" contacts to prevent material delamination, the team fabricated both n-type and p-type nanoribbon channels down to a remarkable 25-30 nanometers in length and width. These devices not only exhibit minimal edge degradation but also deliver record-setting on-state currents, with n-type WS₂ devices showing more than a two orders of magnitude improvement over prior reports. This advance positions top-down patterned 2D nanoribbons as a critical building block for the next generation of nanosheet transistor architectures, promising to extend the era of rapid computational advancement.
This groundbreaking research unequivocally positions monolayer 2D semiconductors as a cornerstone technology for the future of electronics. By achieving unprecedented scaling of nanoribbon transistors down to 25-30 nm channels with record-setting current densities, the collaborative team has provided a critical pathway to extend the foundational principles of Moore's Law well beyond current silicon limitations. The successful demonstration of both n-type and p-type devices, fabricated through a top-down multipatterning process, further underscores the practical viability of these materials for high-performance computing. This advancement moves beyond theoretical promise, presenting tangible results that surpass previous benchmarks, particularly the more than two orders of magnitude improvement observed in WS₂.
The Future of Miniaturization
The broader implications of these findings are profound for an industry constantly seeking increased power and efficiency within ever-shrinking footprints. The ability to design transistors at the atomic limit of thickness, combined with precise nanoscale width and length control, opens the door to creating microprocessors that are not only significantly more compact but also dramatically more energy-efficient. Such advancements are crucial for driving innovation across numerous sectors, from pervasive IoT devices and high-performance computing to advanced AI accelerators and next-generation mobile technology. Moreover, the development of robust, scalable 2D nanoribbon architectures could underpin novel sensor technologies, flexible electronics, and even provide a stable platform for future quantum computing components. While challenges in mass production and complex system integration remain, this research solidifies 2D materials as indispensable building blocks for the sophisticated electronics of tomorrow, charting a clear course for continued technological evolution.