What are CFET and NSFET transistor technologies, and how do they impact future chip design?

CFET (Complementary FET) and NSFET (Nanosheet FET) are advanced transistor architectures being explored for sub-5nm process nodes. These designs aim to significantly improve performance and power efficiency beyond current FinFET technology. NSFETs offer better electrostatic control over the channel, while CFETs integrate n-type and p-type devices compactly. These innovations are critical for continuing Moore's Law, enabling denser, more powerful integrated circuits, and supporting advancements in various computing applications.

How do Rowhammer attacks exploit memory vulnerabilities, particularly in modern GPU architectures?

Rowhammer is a security vulnerability where repeatedly accessing a row of memory can cause electrical interference, leading to bit flips in physically adjacent memory rows. These unintended bit flips can corrupt data or enable unauthorized access. Researchers have demonstrated that these attacks can be amplified using specific non-uniform patterns to exploit ECC-protected GPUs, highlighting ongoing challenges in memory security. Such exploits could compromise the integrity of computations on GPUs, affecting systems from gaming to data centers.

How does concurrent access to host memory and HBM accelerate large language model inference?

Accelerating Large Language Model (LLM) inference requires efficient memory access to handle massive datasets and model parameters. Concurrent access to both High Bandwidth Memory (HBM), typically integrated on-package for high speed, and slower host memory, which offers larger capacity, allows systems to manage increasingly complex models more effectively. By strategically fetching and processing data from both memory types simultaneously, this method reduces latency and improves overall throughput, crucial for deploying advanced LLMs in real-time applications.

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Robotics, Hardware & InfrastructureTuesday, September 29, 2026

Chip Industry Technical Paper Roundup: Sept. 29

Original reporting by Semiconductor Engineering

Semiconductor Engineering’s latest compilation of technical papers reveals the cutting edge of research pushing the boundaries of chip design, manufacturing, and security. The relentless quest for ever-smaller and more powerful transistors takes center stage, with studies evaluating next-generation A7 CFET and A10 NSFET technologies. Complementing this, groundbreaking advancements in wafer-scale sub-5nm MoS₂ transistors promise performance beyond silicon's current limits. As devices grow more complex, advanced packaging becomes critical; research explores multi-kilowatt power delivery for 3D heterogeneous integration and the intricate relationship between copper microstructure and residual stress in Through-Silicon Vias (TSVs), vital for ensuring reliability in stacked architectures.

Advancing Security and AI

Safeguarding these sophisticated systems is equally paramount. New work delves into amplifying Rowhammer attacks on ECC-protected GPUs and sophisticated methods for localizing insidious gate-level RTL Trojans. Simultaneously, the burgeoning field of AI demands novel architectural solutions, exemplified by techniques enabling concurrent High Bandwidth Memory (HBM) and host-memory access to accelerate Large Language Model (LLM) inference. Complementing these hardware innovations, the role of AI extends into the design process itself, with explorations into agent-driven chip design using high-level synthesis (HLS), suggesting a future where intelligent systems play a greater role in creating the chips of tomorrow.

The latest additions to Semiconductor Engineering’s research library illuminate the diverse and intricate challenges currently shaping the industry. From the fundamental quest for sub-5nm logic with A7 CFETs and A10 NSFETs to the groundbreaking development of wafer-scale 2D MoS₂ transistors pushing beyond silicon’s physical limits, innovation at the transistor level remains paramount. Simultaneously, the focus shifts to advanced integration, with critical work on multi-kW power delivery for 3D heterogeneous integration and detailed analyses of copper microstructure in Through Silicon Vias. Furthermore, the imperative for robust security is underscored by research into Rowhammer attacks on GPUs and the demystification of gate-level RTL Trojan localization. Finally, the transformative influence of artificial intelligence is evident in efforts to accelerate LLM inference through concurrent memory access and the pioneering exploration of agent-driven chip design.

A Converging Future Collectively, these advancements suggest a future where semiconductor innovation is profoundly interdependent. The relentless demand for computational power, largely driven by AI and machine learning, is compelling a holistic engineering approach. This means not only pushing the boundaries of materials science and transistor architecture but also mastering complex 3D packaging, ensuring comprehensive hardware security from design to deployment, and leveraging AI itself to automate and optimize the design process. This convergence promises to deliver unprecedented device performance and efficiency, unlocking new capabilities across countless industries. However, it also amplifies the critical need for resilient security infrastructure and ethical AI integration, charting a complex yet exciting trajectory for technological evolution and societal impact well into the future.

Frequently asked questions

What are CFET and NSFET transistor technologies, and how do they impact future chip design?: CFET (Complementary FET) and NSFET (Nanosheet FET) are advanced transistor architectures being explored for sub-5nm process nodes. These designs aim to significantly improve performance and power efficiency beyond current FinFET technology. NSFETs offer better electrostatic control over the channel, while CFETs integrate n-type and p-type devices compactly. These innovations are critical for continuing Moore's Law, enabling denser, more powerful integrated circuits, and supporting advancements in various computing applications.
How do Rowhammer attacks exploit memory vulnerabilities, particularly in modern GPU architectures?: Rowhammer is a security vulnerability where repeatedly accessing a row of memory can cause electrical interference, leading to bit flips in physically adjacent memory rows. These unintended bit flips can corrupt data or enable unauthorized access. Researchers have demonstrated that these attacks can be amplified using specific non-uniform patterns to exploit ECC-protected GPUs, highlighting ongoing challenges in memory security. Such exploits could compromise the integrity of computations on GPUs, affecting systems from gaming to data centers.
How does concurrent access to host memory and HBM accelerate large language model inference?: Accelerating Large Language Model (LLM) inference requires efficient memory access to handle massive datasets and model parameters. Concurrent access to both High Bandwidth Memory (HBM), typically integrated on-package for high speed, and slower host memory, which offers larger capacity, allows systems to manage increasingly complex models more effectively. By strategically fetching and processing data from both memory types simultaneously, this method reduces latency and improves overall throughput, crucial for deploying advanced LLMs in real-time applications.

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